Methods, systems, and computer program product for binding and back annotating an electronic design with a schematic driven extracted view

ABSTRACT

Disclosed are methods, systems, and articles of manufacture for binding and annotating an electronic design with a schematic driven extracted view. These techniques identify a schematic design and an extracted view of an electronic design and bind the schematic design with the extracted view. The resulting binding information concerning binding the schematic design with the extracted view is stored in a data structure. The schematic design may be annotated with extracted view information pertaining to the extracted view based at least in part upon the binding information. A response to a user action may be automatically generated based in part or in whole upon the extracted view information or the binding information.

CROSS REFERENCE TO RELATED APPLICATIONS

This U.S. patent application is cross related to U.S. patent applicationSer. No. 15/721,845 filed concurrently and entitled “METHODS, SYSTEMS,AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING SCHEMATIC DRIVEN EXTRACTEDVIEWS FOR AN ELECTRONIC DESIGN” and U.S. patent application Ser. No.15/721,851 filed concurrently and entitled “METHODS, SYSTEMS, ANDCOMPUTER PROGRAM PRODUCT FOR IMPLEMENTING A NET AS A TRANSMISSION LINEMODEL IN A SCHEMATIC DRIVEN EXTRACTED VIEW FOR AN ELECTRONIC DESIGN”.The contents of the aforementioned U.S. patent applications are herebyexpressly incorporated by reference for all purposes.

COPYRIGHT NOTICE

A portion of the disclosure of this patent document contains material,which is subject to copyright protection. The copyright owner has noobjection to the facsimile reproduction by anyone of the patent documentor the patent disclosure, as it appears in the Patent and TrademarkOffice patent file or records, but otherwise reserves all copyrightrights whatsoever.

BACKGROUND

Modern electronic design is typically performed with computer aideddesign (CAD) tools or electronic design automation (EDA) systems. Todesign an integrated circuit, a designer first creates high levelbehavior descriptions of the IC device using a high-level hardwaredesign language (HDL). Common examples of HDLs include Verilog and VHDL.An EDA system typically receives the high level behavioral descriptionsof the IC device and translates this high-level design language intonetlists of various levels of abstraction. Essentially, the process toimplement an electronic device begins with functional design andverification (e.g., using RTL), and then proceeds to physical design ofa layout and verification.

Circuit designers and verification engineers use different methods toverify circuit designs. One common method of verification is throughsimulation of the circuit design of interest. Simulation dynamicallyverifies a design by monitoring behaviors of the design with respect totest stimuli. For many types of designs, simulation can and should beperformed during the design process to ensure that the ultimate goalsare achievable and will be realized by the finished product.

SPICE (Simulation Program with Integrated Circuit Emphasis) is a commontype of simulator that is used to simulate and verify the operation ofan electronic design. With SPICE, the electronic design is convertedinto a system of equation(s), which is then solved for a given set ofinputs to check the state of specific portions of the circuit at givenpoints in time. Furthermore, capturing the electrical behaviors of acircuit design requires correctly modeling various components of acircuit design to include, for example, geometric information, parasiticinformation, etc. Although many vendors provide, for example, SPICEmodels, s-parameter models, etc. for their devices, an IC design or asystem design may involve much more than merely these device models forsimulation. For example, the packaging may need to be properlyaccommodated in such models, the traces or interconnects may need to bemodeled to reflect more realistic voltage drops, etc. For many circuitdesigns, this process can be a very computationally expensive andtime-consuming effort, especially given the size and complexity ofmodern circuit designs.

Conventional approaches for simulations, especially for board or systemlevel simulations (e.g., simulations performed on an electronic systemincluding the printed circuit board or PCB, one or more integratedcircuit (IC) chips, and IC packaging thereof) often extract a staticsimulation view from layouts (e.g., IC layout, package layout, boardlayout, etc.) by identifying a corresponding schematic symbol from theschematic symbol library for each of a plurality of layout circuitdevices, invoking the corresponding layout editor, and performing theextraction therein. The extraction results are then saved as sometextual form (e.g., an ASCII file for a SPICE netlist). As a result,these simulation views are often termed layout extracted views or simplyextracted views; and they are understandable by the simulators but notmuch more beyond that. That is, the graphical representations or asimplified version thereof representing how circuit components areconnected may be lost in the generation of these conventional extractedviews. The electronic design may then undergo multiple rounds of changesto the schematic, the layout, or both the schematic and the layout afterthe initial simulation has been performed with a simulation viewextracted from the initial layout.

When these changes occur at the schematic level, these conventionalapproaches require a designer to implement the changes in the schematicof the electronic design, push these schematic changes to create anupdated layout with a layout editor, and then extract an updatedsimulation view with the updated layout. The simulator may then performanother round of simulation with the updated simulation view. This loopnot only requires much more time and computational resources but alsopresents multiple other problems.

For example, modern electronic design may include devices havingdistributed pins, vector pins, etc. that may be represented as an inputpin in the schematic symbol. During a simulation of, for example, anelectronic design with a distributed Vcc having multiple Vcc pins for adistributed power network, this distributed Vcc may be schematicallyrepresented as a single Vcc pin in the corresponding schematic symbol.In this example, if the simulation result for the Vcc shows abnormalbehavior the designer will need to guess which Vcc pin or Vcc pins arecausing the abnormal behavior or perform some trial-and-error changes toidentify the true cause of the abnormal behavior. Similar problems andhence challenges also arise for vector pins which may be even moredifficult to troubleshoot and identify the root source of any abnormalbehavior simulation result due to the multiplicity of the pins.

Another problems with these conventional approaches is that theextracted view from a layout is a static view. These simulation viewsare generated by traversing a layout to identify layout componentdesigns and devices, identify a corresponding schematic symbol for eachof the layout component designs, place the schematic symbol in thesimulation view, and interconnect the schematic symbols by referencingthe layout connectivity. Although these simulation views may in somecases appear to be identical or substantially similar to the originalschematic from which the layout is generated, these simulation views orextracted views are not editable as the original schematic. As a result,any changes at the schematic level must go through the aforementionedschematic edit, layout edit, and re-extraction.

Moreover, these simulation views are often generated for the simulationengines and thus do not appear as readable or understandable bydesigners. More importantly, these extracted views are generated as aflat view having a single hierarchy that includes all the schematicsymbols or models understood by the simulation engine. As a result, anextracted view loses the hierarchical structures of the electronicdesigns; and the loss of the hierarchical structure further exacerbatesthe difficulties in understanding or manipulating such an extractedview, even if the extracted view were to be editable.

Another problem with conventional approaches is that the same schematicsymbol may correspond to multiple schematic instances in the schematicdesign and hence multiple layout instances in the layout. During thegeneration of an extracted view from the layout in conventionalapproaches, these multiple layout instances may be extracted andrepresented as the same schematic symbol whereas these multiple layoutinstances may not necessarily be identically implemented in the layout.For example, two or more of these multiple layout instances may berouted differently although then all correspond to the same schematicsymbol. As a result, conventional simulation views cannot correctcapture the differences in, for example, parasitics and/or electricalcharacteristics between these layout instances.

In addition to the aforementioned problems, what actually predicts thepredicted behaviors is the extracted views because these extracted viewsmodel at least the components that may affect the electrical behaviorsof the underlying circuit. Nonetheless, designers and users of variouselectronic design tools are more used to view and interact withschematic designs because a schematic design delineates how circuitcomponents are interconnected with each other although the schematicdesign may not indicate or even imply the scales or sizes of thesecircuit component designs. As described above, conventional extractedviews are obtained from various layouts and are created in a form (e.g.,ASCII file) that is understood by the simulators (e.g., SPICEsimulators) but not the users, at least not in a graphical way thatresembles how circuit component designs are interconnected. Althoughthese extracted views may be back annotated or associated with theunderlying schematic, these extracted views are not intuitive and notunderstandable unless the users parse through the textual descriptiontherein. Moreover, even if users can parse through these extracted viewsand understand their contents, these conventional extracted views oftencluttered the design space and thus provide not much value, if any atall, for users to perform their intended tasks.

At Giga-hertz (GHz) frequencies, long interconnect leads may exhibittransmission line behavior because of the fast rise/fall times ofsignals. Moreover, with the use of wider wires, inductive impedance(jωL) at high frequencies (e.g., microwave, RF or radio frequency, etc.)becomes comparable to the resistive component (R) of the major signalwires and power/ground nets. For copper wires, this phenomenon becomeseven more prominent. Such parasitic inductance may cause additionalsignal delays, over-shoot waveforms, increased ground bounce, andinductive crosstalk so clock trees and the power/ground grids need to bedesigned more carefully to avoid large clock skew, signal inductivecoupling, ground bounce, etc.

Conventional approaches merely consider the inductive effects ofinterconnect leads only for a few global clock wires and major signalbuses. This has been proved to be insufficient because of higher clockfrequencies and faster signal rise/fall times. Three-dimensional (3D) ortwo-and-a-half (2.5D) electromagnetic (EM) full wave field solvers areavailable but do not have the capacity to manage modern ICs and oftenbecome prohibitively expensive, especially those having large, complexcircuits. These problems and challenges are in addition to thosepertaining to conventional, layout-driven extracted views.

Thus, what are needed are methods, systems, and computer programproducts for binding and annotating an electronic design with aschematic driven extracted view to address at least the aforementionedissues and shortcomings.

SUMMARY

Disclosed are method(s), system(s), and article(s) of manufacture forbinding and annotating an electronic design with a schematic drivenextracted view in one or more embodiments. Some embodiments are directedat a method for binding and annotating an electronic design with aschematic driven extracted view.

In some embodiments, these techniques identify a schematic design and anextracted view of an electronic design and bind the schematic designwith the extracted view. The resulting binding information concerningbinding the schematic design with the extracted view is stored in a datastructure. The schematic design may be annotated with extracted viewinformation pertaining to the extracted view based at least in part uponthe binding information. A response to a user action may beautomatically generated based in part or in whole upon the extractedview information or the binding information.

In some of these embodiments, a layout of the electronic design mayfurther be identified, and the user action may include a probing actionthat obtains one or more electrical characteristics of the schematicdesign. To generate a response to the user action, a first userselection of a first schematic circuit component design may beidentified in the schematic design; and a first model corresponding tothe first schematic circuit component design may be emphasized in theextracted view or a model tree structure in response to the first userselection.

In some of these embodiments, a second user selection of a second modelmay be identified in the extracted view; and a second schematic circuitcomponent design corresponding to the second model may be emphasized inthe schematic design or a schematic design tree structure in response tothe second user selection.

In some embodiments where a response is generated to a user action, aschematic circuit component design corresponding to the user action maybe identified; a model corresponding to the schematic circuit componentdesign may also be identified from the extracted view; and a type forthe schematic circuit component design may be determined.

Based in part or in whole upon the type or the model that corresponds tothe schematic circuit component design, a point of interest may beidentified in the schematic design. One or more electricalcharacteristics at the point of interest may be identified by using atleast the extracted view; and the one or more electrical characteristicsmay be presented in a user interface.

In some embodiments, disambiguation processing may be performed inresponse to the user action based at least in part upon the type for theschematic circuit component design. In addition or in the alternative,error handling processing may be performed in response to the useraction based at least in part upon the type for the schematic circuitcomponent design.

Some embodiments are directed at a hardware system that may be invokedto perform any of the methods, processes, or sub-processes disclosedherein. The hardware system may include at least one processor or atleast one processor core, which executes one or more threads ofexecution to perform any of the methods, processes, or sub-processesdisclosed herein in some embodiments. The hardware system may furtherinclude one or more forms of non-transitory machine-readable storagemedia or devices to temporarily or persistently store various types ofdata or information. Some exemplary modules or components of thehardware system may be found in the System Architecture Overview sectionbelow.

Some embodiments are directed at an article of manufacture that includesa non-transitory machine-accessible storage medium having storedthereupon a sequence of instructions which, when executed by at leastone processor or at least one processor core, causes the at least oneprocessor or the at least one processor core to perform any of themethods, processes, or sub-processes disclosed herein. Some exemplaryforms of the non-transitory machine-readable storage media may also befound in the System Architecture Overview section below.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings illustrate the design and utility of various embodiments ofthe invention. It should be noted that the figures are not drawn toscale and that elements of similar structures or functions arerepresented by like reference numerals throughout the figures. In orderto better appreciate how to obtain the above-recited and otheradvantages and objects of various embodiments of the invention, a moredetailed description of the present inventions briefly described abovewill be rendered by reference to specific embodiments thereof, which areillustrated in the accompanying drawings. Understanding that thesedrawings depict only typical embodiments of the invention and are nottherefore to be considered limiting of its scope, the invention will bedescribed and explained with additional specificity and detail throughthe use of the accompanying drawings in which:

FIG. 1 illustrates a high level block diagram of a simplified system forbinding and annotating an electronic design with a schematic drivenextracted view in one or more embodiments.

FIG. 2A illustrates a high level block diagram for binding andannotating an electronic design with a schematic driven extracted viewin one or more embodiments.

FIG. 2B illustrates more details about a portion of the high level blockdiagram illustrated in FIG. 2A in one or more embodiments.

FIG. 2C illustrates more details about a portion of the high level blockdiagram illustrated in FIG. 2A in one or more embodiments.

FIG. 3A illustrates an example of a simplified schematic design that isto be bound to and annotated with extracted view information from anextracted view in one or more embodiments.

FIG. 3B illustrates an example of a model that may be used to representa schematic circuit component design in an extracted view and to backannotate an electronic design in one or more embodiments.

FIG. 3C illustrates an example of an extracted view including a modelthat represents a schematic circuit component design of interest in oneor more embodiments.

FIG. 3D illustrates an example of the schematic design illustrated inFIG. 3A that is bound to and annotated with some extracted viewinformation from an extracted view in one or more embodiments.

FIG. 4A illustrates an example of another schematic design that is to bebound to and annotated with extracted view information from an extractedview in one or more embodiments.

FIG. 4B illustrates an example of an intermediate stage during thegeneration of an extracted view for the schematic design illustrated inFIG. 4A in one or more embodiments.

FIG. 4C illustrates an example of an extracted view that may bereferenced in annotating the schematic design illustrated in FIG. 4A inone or more embodiments.

FIG. 4D illustrates an example of a model annotator dialogue window forannotation of and binding with an electronic design in one or moreembodiments.

FIG. 4E illustrates an example of another extracted view that may bereferenced for annotation of and binding with an electronic design inone or more embodiments.

FIG. 4F illustrates an example of a simplified schematic design to whichthe model annotation and binding may be applied with reference to theextracted view illustrated in FIG. 4E in one or more embodiments.

FIG. 4G illustrates an example of a simplified model annotation browserfor the extracted view illustrated in FIG. 4E and the simplifiedschematic design illustrated in FIG. 4F in one or more embodiments.

FIG. 4H illustrates another example of another extracted view that maybe referenced for annotation of and binding with an electronic design inone or more embodiments.

FIG. 4I illustrates another example of a simplified schematic design towhich the model annotation and binding may be applied with reference tothe extracted view illustrated in FIG. 4H in one or more embodiments.

FIG. 4J illustrates another example of a simplified model annotationbrowser for the extracted view illustrated in FIG. 4H and the simplifiedschematic design illustrated in FIG. 4I in one or more embodiments.

FIG. 4K illustrates an example of a schematic design and an extractedview that may be referenced for annotation of and binding with theschematic design in one or more embodiments.

FIG. 4L illustrates some examples of extracted view information that maybe annotated with or bound to an electronic design in one or moreembodiments.

FIG. 5 illustrates a computerized system on which a method for bindingand annotating an electronic design with a schematic driven extractedview may be implemented.

DETAILED DESCRIPTION

Various techniques are directed to binding and annotating an electronicdesign with a schematic driven extracted view in various embodiments. Inthese embodiments, a schematic-driven extracted view of an electronicdesign is identified. This extracted view may include one or more modelsrepresenting one or more corresponding schematic circuit componentdesigns. A binding may be established between at least two of theschematic design, the corresponding layout, an extracted view, the oneor more models in the extracted view, the one or more correspondingschematic circuit component designs, and/or one or more correspondinglayout circuit component designs. The resulting binding information maybe stored in a data structure that may be further indexed (e.g., with aunique key such as a unique identifier) to facilitate faster access toand retrieval of information from the data structure.

With the extracted view and the binding, the schematic design and/or thelayout may be annotated with various types of information to facilitatevarious EDA (electronic design automation) tasks such as probing,testing, modification, fine-tuning, optimization, etc. to prepare theunderlying electronic design or to finalize the electronic design formask preparation and mask writing as well as for tapeout for theeventual manufacturing of the electronic circuits represented by theelectronic design.

Various embodiments will now be described in detail with reference tothe drawings, which are provided as illustrative examples of theinvention so as to enable those skilled in the art to practice theinvention. Notably, the figures and the examples below are not meant tolimit the scope of the present invention. Where certain elements of thepresent invention may be partially or fully implemented using knowncomponents (or methods or processes), only those portions of such knowncomponents (or methods or processes) that are necessary for anunderstanding of the present invention will be described, and thedetailed descriptions of other portions of such known components (ormethods or processes) will be omitted so as not to obscure theinvention. Further, various embodiments encompass present and futureknown equivalents to the components referred to herein by way ofillustration.

FIG. 1 illustrates a high level block diagram of a simplified system forbinding and annotating an electronic design with a schematic drivenextracted view in one or more embodiments. In this illustrated system,one or more computing systems 100A may invoke and execute variousmodules to identify an extracted view 106A for an electronic design.These one or more computing systems may further identify, for example, aschematic design 102A, a layout (not shown), etc. and bind the extractedview 106A, one or more models (e.g., the model 108A representingschematic circuit component design 104A in the schematic design 102A)therein, and/or various types of extracted view information pertainingto the extracted view 106A and/or to the one or more models therein withthe schematic design 102A, the layout, etc.

These one or more computing systems 100A may further annotate (e.g.,back annotate 138A) the electronic design (e.g., the schematic design102A) with various types of information to facilitate the performance ofvarious tasks or operations on the schematic design 102A. For example, auser may probe or select the schematic circuit component design 104A (asshown by two graphically emphasized net segments) in the schematicdesign 102A, and the binding (130A, 132A, and 134A) between theschematic design 102A and the extracted view 106A may automatically showthe extracted view 106A with the corresponding model 108A highlighted inthe extracted view. The binding may further provide the capability ofgraphically and/or textually emphasizing the corresponding circuitcomponent designs or models 112A in an annotation browser 110A showingthe hierarchical structure in response to the selection of the schematiccircuit component design 104A.

With various types of extracted view information annotated in theelectronic design (e.g., the schematic design 102A although other typesof the electronic design may also be annotated), a user may have muchbetter access to such design-related information (e.g., electricalbehaviors, parasitic data, timing data, electrical/physical/geometricdata, etc.) to further facilitate the performance of various tasks onthe schematic design. For example, a user may probe a point or aschematic design circuit component design, and the system mayautomatically identify the corresponding pertinent data (e.g.,electrical behaviors) obtained through simulating the extracted view andpresent the corresponding pertinent data to the user.

In some cases where the probing location or schematic design circuitcomponent design does not definitely identify a single response, thesystem may further respond to the user's probing action with a question.For example, a user may probe a net (e.g., by clicking on the net 104A)to seek voltage information. The system may respond by asking the userto determine whether the user would like to obtain the voltageinformation at the capacitor end or at the resistor end of net 104A byusing the binding information. Based on the user's additional input, thesystem may retrieve and present the pertinent voltage information to theuser.

As described above, the one or more computing systems 100A may invokeand execute one or more modules to perform various intended functions.Each of these modules may be implemented as a pure hardwareimplementation (e.g., in the form of firmware, application specific IC,etc.), a pure software implementation, or a combination of hardware andsoftware implementation. In some embodiments where a module isimplemented at least partially as a software implementation, the modulemay be stored at least partially in memory (e.g., in random accessmemory, instruction cache, etc.) of at least one of these one or morecomputing systems 100A for execution.

These modules may include one or more EDA (electronic design automation)modules 136A such as a schematic tool, a placement tool, a routing tool,verification tools, post-route or post-layout optimization tools,various photolithography tools (e.g., optical proximity correction orOPC tools, phase shift mask or PSM tools, resolution enhancementtechnology or RET tools, etc.), etc. to prepare the electronic designfor finalizing the electronic design for mask preparation and maskwriting as well as for tapeout for the eventual manufacturing of theelectronic circuits represented by the electronic design.

These models may also include extracted view modules 120A that mayinclude, for example, one or more model annotator modules that areconfigured to annotate an electronic design abstraction with informationpertaining to one or more extracted views corresponding to theelectronic design abstraction. The extract view modules 120A may furtherinclude 3D and/or 2.5D modeling tools to model various components in the3D or 2.5D space, extraction modules to extract geometric, physical,and/or electrical characteristics, properties, or attributes fromvarious sources (e.g., layouts, SEM or scanning electron microscopephotos, etc.), meshing module(s) to discretize an area or a volume intoa plurality of meshes, and/or one or more geometry simplification orreduction modules to simplify geometries by approximating more complexgeometries with simpler geometries (e.g., by approximating a curve witha plurality of straight segments depending upon the resourcerequirements and/or the accuracy requirements).

The extracted view modules 120A may also include one or more EM(electromagnetic) field solver modules, heuristic solver modules, and/toempirical formula solver modules to solve for the electrical behavior ofan underlying electronic circuit. The extracted view modules 120A mayfurther include a pre-layout exploration module that estimates thecharacteristics, attributes, and/or properties of a circuit componentdesign, without invoking any layout editors.

These one or more computing systems 100A may further access a schematicdesign database 118A and a layout database 116A when generating anextracted view from a schematic design of an electronic design. Aplurality of models (e.g., SPICE sub-circuits, IBIS models, s-parametermodels, etc.) and/or parasitic data 122A may also be stored and madeavailable to these one or more computing systems.

For example, some embodiments may store parasitic data of someparameterized, pre-existing, or pre-characterized electronic circuitcomponent designs in a tabular structure (e.g., a database) so thatthese one or more computing systems, when modeling an electronic circuitcomponent design as model in an extracted view, may look up theparasitic data, model data, or even a parameterized model for asubstantially similar or previously characterized electronic circuitcomponent design so that these one or more computing systems 100A nolonger need to expend as much or any computational resources inconstructing the model for the electronic circuit component design.

FIG. 2A illustrates a high level block diagram for binding andannotating an electronic design with a schematic driven extracted viewin one or more embodiments. In these illustrated embodiments, aschematic design of an electronic design and an extracted view derivedfrom the schematic design may be identified at 202A. In some of theseembodiments, the corresponding layout of the underlying electronicdesign may also be optionally identified at 202A.

A binding may be established at 204A between the schematic design andthe extracted view. The binding may include links between the schematicdesign and the extracted view in some embodiments and links between oneor more schematic circuit component designs and one or morecorresponding models (e.g., s-parameter models, IBIS models,transmission line models, SPICE sub-circuits, any combinations thereof,etc.) in some other embodiments.

With the binding established, the schematic design may be back annotatedat 206A with extracted view information pertaining to the extracted viewbased in part or in whole upon binding information about the bindingbetween the schematic design and the extracted view. The extracted viewinformation pertaining to the extracted view may include, for example,various pieces of information or data about the extracted view and/orone or more abstractions (e.g., the schematic designs, the layouts, etc.in one or more design fabrics) of the underlying electronic design,electrical behaviors, parasitic data, timing data,electrical/physical/geometric data of various circuit design components,information about the models and their respective model components inthe extracted view, or any other data pertaining to the extracted viewor the underlying electronic design.

A response may be generated at 208A in response to a user actionperformed on or for the schematic design based in part or in whole uponthe annotations and/or the binding between the schematic design and theextracted view. In these embodiments, these techniques leverage thebinding as well as the annotations to automatically generate a responseto a user's action to facilitate design closure and the eventual maskwriting as well as the manufacturing of the underlying electronicdesign. A user action may include, for example, a modification action tomodify the schematic design, a probing action to obtain informationabout a specific portion of the schematic design, a selection oridentification of a schematic circuit component design or a portion(e.g., a node, a net segment, etc.) thereof.

FIG. 2B illustrates more details about a portion of the high level blockdiagram illustrated in FIG. 2A in one or more embodiments. Morespecifically, FIG. 2B illustrates more details about generating aresponse at 208A of FIG. 2A. For the ease of description andillustration, an example of a user's selection or identification of aschematic circuit component design is described with reference to FIG.2B. It shall be noted that these techniques may also generate anautomatic response to other types of user actions, and that thedescription of a user's selection or identification of a schematiccircuit component design is not intended to limit the scope of theclaims or the scope of such other types of user actions.

In these illustrated embodiments, a user's selection or identificationof a first circuit component design may be identified at 202B. Thisfirst circuit component design may include a schematic circuit componentdesign identified from a schematic design or a model included in theextracted view. For example, a user may simply click on a node or aportion of the schematic circuit component design in a user interfaceshowing the schematic design. As another example, a user may inquireinto some design related information (e.g., electrical behavior) about aschematic circuit component design. In this latter example, theschematic circuit component design may also be identified as the firstschematic circuit component design at 202B.

Similarly, a model in the extracted view may also be identified at 202Bwhen user clicks on the model in the extracted view. For the ease ofdescription and illustration, FIG. 2B will be described with referenceto a model being identified from the extracted view although theidentification of the first circuit component design may be performed invarious types of the electronic design—the schematic design, the layout,or the extracted view.

A first model, if any, corresponding to the identified schematic circuitcomponent design may be graphically and/or textually emphasized at 204Bin the extracted view or a model tree structure (e.g., a hierarchystructure listing the model components of the model). In theseembodiments, a user identifies the first schematic circuit componentdesign, and the system automatically invokes the extracted view andgraphically and/or textually emphasizes the model corresponding to theidentified schematic circuit component design so that the userunderstands whether the identified schematic circuit component designhas been represented by a model for analysis modules, and if so, whichmodel is used to represent the identified schematic circuit componentdesign.

In some of these embodiments, other annotated information (e.g., thecontents of the model, electrical behaviors, etc.) may also be presentedto the user in response to the identification or selection of theschematic circuit component design. For example, the first model mayinclude one or more additional schematic circuit component designs inaddition to the identified schematic circuit component design. In thisexample, these one or more additional schematic circuit componentdesigns may also be graphically and/or textually emphasized in theschematic design with the same emphasis scheme or with a differentemphasis scheme to distinguish the identified schematic circuitcomponent design from these one or more additional schematic circuitcomponent designs.

In some embodiments, a user's selection or identification of a secondmodel in the extracted view may be identified at 206B. For example, auser may click on the second model in the extracted view, and the secondmodel may be identified at 206B.

In response to this user's selection or identification the second modelin the extracted view, the second schematic circuit component design maybe identified and may be further textually and/or graphically emphasizedat 208B in the schematic design or in a hierarchical schematic designdata structure. In these embodiments illustrated in 206B and 208B, auser may select a model in an extracted view, and the correspondingschematic circuit component design can be automatically shown in theschematic design so that the user understands which schematic circuitcomponent designs are modeled and incorporated in the selected model.This understanding may help the user to select a more accurate orprecise point or portion in the schematic design to probe, test, ortroubleshoot the schematic design.

FIG. 2C illustrates more details about a portion of the high level blockdiagram illustrated in FIG. 2A in one or more embodiments. Morespecifically, FIG. 2C illustrates more details about generating aresponse at 208A of FIG. 2A. In these illustrated embodiments, aschematic circuit component design that corresponds to a probing actionmay be identified at 202C. The probing action includes, for example, thedetermination or obtaining of electrical characteristics (e.g., voltagevalues, current, etc.) at a specific location or through a specificportion of a circuit component design.

A type of the schematic circuit component design may be determined at204C. Some examples of types of schematic circuit component designsinclude device pins, distributed pins (e.g., distributed Vdd pins,distributed ground pins, etc.) that are collectively represented as asingle logical pin in a schematic design, vector pins, a net or a netsegment, etc.

The type of the identified schematic circuit component design may affecthow the system responds to the identification or selection of theschematic circuit component design. For example, if a logical pincorresponds to a single physical pin, the voltage value from performingan electrical analysis on the extracted view may be identified for thesingle physical pin in the extracted view when a user probes a singlelogical pin for its voltage. On the other hand, if a single logical pinin the schematic design corresponds to multiple physical pins in theextracted view, the system's response to the identification or selectionof this single logical pin may be different. For example, the system mayrespond by showing all the voltage values of all these multiple physicalpins in some embodiments or further asking the user to identify whichphysical pin the user intended to probe in some other embodiments.

As another example, the system may respond by issuing an error messagewhen a user attempts to probe a net that is fully enclosed within amodel to indicate that such a probing action is not allowed. The systemmay further present which model component corresponds to the identifiednet in some of these embodiments. On the other hand, when the identifiednet is represented as a model interface (e.g., input to or output fromanother model component), the system may further ask the user toidentify which end of the net the user intended to probe in someembodiments or may present the pertinent information (e.g., voltagevalues) at both ends of the identified net.

A point of interest may be identified at 206C in the schematic designbased in part or in whole upon the type of the schematic circuitcomponent design and also on the model that corresponds to theidentified schematic circuit component design. This point of interestmay be identified automatically when the system may definitely determinea single point of interest corresponding to the identification orselection of the schematic circuit component design at 202C. In someother embodiments where the system cannot definitely determine a singlepoint of interest corresponding to the identification or selection ofthe schematic circuit component design, the system may further presentan interactive dialogue box or window to seek further input orclarification from the user in some embodiments. In some otherembodiments, the system may simply present the pertinent information(e.g., probed electrical behavior) of all the candidate points for theidentified schematic circuit component design to the user.

One or more electrical characteristics may be identified at 208C from,for example, analysis results of one or more analyses performed on theextracted view for the identified point of interest. These one or moreelectrical characteristics may be presented in a user interface.

A conventional schematic design does not necessarily include sufficientinformation (or any information at all) to guide a user in selecting,identifying, or probing schematic circuit component designs. In someembodiments, error handling may be performed at 210C based at least inpart upon the type(s) of schematic circuit component designs. Forexample, a schematic circuit component design that is fully enclosed ina model may not be directly probed in some embodiments. Nonetheless, auser may incidentally select this schematic circuit component design. Insome embodiments, intelligence may be built into the system so that whena fully enclosed schematic circuit component design is selected, awarning message is issued to indicate that this selected schematiccircuit component design cannot be directly probed, and this warningmessage may be issued even before the user issues the probing command.

In some embodiments where the schematic circuit component design is notidentified in such a way to instruct the system to definitely determinea response, a disambiguation process may be performed to identifyadditional information so that the system may definitely determine aresponse. In an example involving a distributed pin that is representedas a single logical pin in a schematic design but corresponds tomultiple physical pins in the layout, the disambiguation process mayfurther ask a user to clarify which physical pin the user would like toselect, or whether the user would like to obtain the results for all thephysical pins. In some embodiments, the disambiguation process maysimply present the results of all the physical pins of the net to theuser.

In another example where a net is incorporated into a model as aninterface of the model, the disambiguation process may ask the user toclarify which end of the net the user would like to select, or whetherthe user would like to obtain the results for both ends of the net. Insome embodiments, the disambiguation process may simply present theresults of both ends of the net to the user. In some embodiments where auser directly issues a probing command on a schematic circuit componentdesign for which multiple values of a characteristic exist, thedisambiguation process may also intervene to either ask for additionalclarification or to present all of these multiple values with respectivedistinguishing information (e.g., respective physical pin identifiers).

FIG. 3A illustrates an example of a simplified schematic design that isto be bound to and annotated with extracted view information from anextracted view in one or more embodiments. This example schematic design300A includes two nets of interest 302A and 304A and is subject to thebinding and annotation operations described above with reference toFIGS. 1 and 2A-2C.

FIG. 3B illustrates an example of a model that may be used to representa schematic circuit component design in an extracted view and to backannotate an electronic design in one or more embodiments. Morespecifically, FIG. 3B shows the symbol 302B that may be used torepresent the net of interest 302A in an extracted view. This symbol302B may be created anew or modified from an existing schematic symbol.Moreover, this symbol 302B includes two interfaces 304B and 306B thatmay be used to interconnect this symbol to the corresponding portions inthe extracted view in such a way to graphically resemble the originalschematic design (e.g., 300A in FIG. 3A).

In addition, FIG. 3B further illustrates a simplified example of atransmission line model 308B including two interfaces 310B and 312B thatrespectively correspond to the interfaces 306B and 304B of the symbol302B. This simplified example of transmission line model 308B furtherincludes transmission line model components 314B (a straight linesegment), 316B (a 90-degree bend), and 318B (another straight linesegment) that are interconnected with each other and with the interfaces310B and 312B.

FIG. 3C illustrates an example of an extracted view including a modelthat represents a schematic circuit component design of interest in oneor more embodiments. More specifically, FIG. 3C illustrates the examplewhere the transmission line model 302B is placed and interconnected withstraight flight-line segments 302C and 304C. A snapshot may be takenfrom this modified schematic design 300C and saved as an extracted viewthat may be referenced in back annotating the schematic design 300A.

FIG. 3D illustrates an example of the schematic design illustrated inFIG. 3A that is bound to and annotated with some extracted viewinformation from an extracted view in one or more embodiments. Morespecifically, FIG. 3D illustrates that the schematic design 300Aincluding the nets of interest 302A and 304A is back annotated with theextracted view (e.g., 300C in FIG. 3C) via binding the extracted view tothe schematic design or vice versa. FIG. 3D also graphically illustratesthe binding between the net of interest 302A and the corresponding model302B (e.g., a transmission line model) that is used to represent the net302A in the extracted view 300C.

The model 302B and/or information pertaining to the model 302B may beback annotated in the schematic design 300A in the form of annotationsalthough it shall be noted that annotations in an electronic design mayor may not necessarily always be shown in the user interface showing theelectronic design. Rather, any of these annotations may be shown in thesame user interface or in a separate user interface (e.g., a pop-upwindow, another electronic design user interface, etc.) on an on-demandbasis. Moreover, FIGS. 3A and 3C-3D also illustrate that when onecomponent is selected in one design abstraction, the selected componentas well as its corresponding component may be graphically and/ortextually emphasized. For example, when a user selects the net 302A inthe schematic design 300A (in FIG. 3A or 3D), the bound model 302B mayalso be highlighted in the extracted view 300C in FIG. 3C and 302B inthe schematic design 300A as shown in FIG. 3D if the schematic design isconfigured to shown the annotated models.

FIG. 4A illustrates an example of another schematic design that is to bebound to and annotated with extracted view information from an extractedview in one or more embodiments. In this example, the schematic designincludes a schematic cell 400A that is operatively connected to foursets of schematic circuit component designs. Each set of schematiccircuit component design includes a first net (e.g., 402A1 or the firstnet N1, 402A2 or the fourth net N4, 402A3 or the seventh net N7, and402A4 or the tenth net N10) connected to a first resistor (e.g., 404A1or the first resistor R1, 404A2 or the second resistor R2, 404A3 or thethird resistor R3, and 404A4 or the fourth resistor R4) in series.

The first resistor in each set is further connected to a second net(e.g., 406A1 or the second net N2, 406A2 or the fifth net N5, 406A3 orthe eighth net N8, and 406A4 or the eleventh net N11) which is in turnedconnected to a first capacitor (e.g., 408A1 or the first capacitor C1,408A2 or the second capacitor C2, 408A3 or the third capacitor C3, and408A4 or the fourth capacitor C4). The first capacitor in each set ofschematic circuit component designs is then connected to the schematiccell 400A.

FIG. 4B illustrates an example of an intermediate stage during thegeneration of an extracted view for the schematic design illustrated inFIG. 4A in one or more embodiments. More specifically, FIG. 4Billustrates an intermediate stage at which the schematic circuitcomponent designs 406A1 (the second net N2), 406A2 (the fifth net N5),408A3 (the eighth net N8), 404A4 (the fourth resistor R4), 406A4 (theeleventh net), and 408A4 (the fourth capacitor C4) are removed from theschematic design.

The schematic design symbols of the other schematic component designsare retained in the schematic design. The retention of a schematicdesign symbol in a schematic design may indicate that the schematiccircuit component design is also retained in some embodiments, or that amodel actually replaces the schematic circuit component design yet usesthe same schematic symbol in some other embodiments. These removedschematic circuit component designs will be represented with models inthe extracted view as described above.

FIG. 4C illustrates an example of an extracted view that may bereferenced in annotating the schematic design illustrated in FIG. 4A inone or more embodiments. In this example, three models 402C, 404C, and406C are inserted and placed in the schematic design. For example, model402C is inserted into the schematic design to replace net segment 406A1(the second net N2); model 404C is inserted into the schematic design toreplace net segment 406A2 (the fifth net N5) and net segment 406A3 (theeighth net N8); and model 406C is inserted into the schematic design toreplace resistor 404A4 (the fourth resistor R4), the net segment 406A4(the eleventh net N11), and capacitor 408A4 (the fourth capacitor C4).

In addition, each of these three models is properly interconnected withthe corresponding portion of the schematic design by using connectivityinformation (e.g., schematic connectivity information and/or layoutconnectivity information) in an identical or substantially similarmanner as described above with reference to the U.S. patent applicationslisted in the section entitled Cross Reference to Related Applications.

FIG. 4D illustrates an example of a model annotator dialogue window forannotation of and binding with an electronic design in one or moreembodiments. In this example, the model annotator dialogue window 400Dincludes the models 402D, 404D, and 406D in the extracted view. Thismodel annotator dialogue window 400D further illustrates thehierarchical structure of the extracted view where the three models S1(402D), S2 (404D), and S4 (406D) are hierarchically placed under thehierarchy entitled “TOP”. Moreover, this model annotator dialogue window400D further illustrates optionally annotating a portion of theschematic design located at a specific hierarchy. For example, FIG. 4Dillustrates that the “MID-block” hierarchy in the schematic design isalso annotated with another model S12 (408D).

In addition, FIGS. 4A and 4C-4D also illustrate that when one componentis selected in one design abstraction, the selected component as well asits corresponding component may be graphically and/or textuallyemphasized. For example, when a user selects the nets 406A2 and 406A43in the schematic design (in FIG. 4A), the bound model 404C may also behighlighted in the extracted view in FIG. 4C and 404D in the modelannotator 400D as shown in FIG. 4D. Alternatively, a user may select themodel 404C in the extracted view illustrated in FIG. 4C (or the model“S2” (404D) in the model annotator 400D in FIG. 4D), and thecorresponding schematic circuit component designs 406A2 and 406A4 may beidentified via the binding information described above and graphicallyand/or textually emphasized in the schematic design illustrated in FIG.4A.

As another working example of the binding between various abstractionsof the electronic design, a user may probe, for example, the fifth net(N5) 406A2 that is incorporated into the model 404C as two of the fourinterfaces to the external circuitry. For example, a use may select thefifth net 406A2 and instruct the system to provide electrical behaviorinformation such as a voltage value. The identification of the fifth net406A2 corresponds to more than one candidate voltage values so thesystem cannot deterministically determine which voltage value toretrieve. In some embodiments, the system may further inquire into whichend of the second net (the second resistor 404A2 end or the secondcapacitor 408A2 end) the user would like to obtain the electricalbehavior information for. In some other embodiments, the disambiguationmodule may provide both voltages at both ends of the fifth net 406A2 inresponse to the identification of the fifth net. In some otherembodiments, the disambiguation module may further provide transientbehavior information (e.g., waveforms) and/or distribution of therequested information along the identified schematic circuit componentdesign.

FIG. 4E illustrates an example of another extracted view that may bereferenced for annotation of and binding with an electronic design inone or more embodiments. More specifically, FIG. 4E illustrates the sameextracted view as that illustrated in FIG. 4C.

FIG. 4F illustrates an example of a simplified schematic design to whichthe model annotation and binding may be applied with reference to theextracted view illustrated in FIG. 4E in one or more embodiments. Morespecifically, FIG. 4F illustrates the same schematic design as thatillustrated in FIG. 4A described above.

FIG. 4G illustrates an example of a simplified model annotation browserfor the extracted view illustrated in FIG. 4E and the simplifiedschematic design illustrated in FIG. 4F in one or more embodiments. Morespecifically, FIG. 4G illustrates the same model annotator 400D asillustrated in FIG. 4D described above.

In this example, FIGS. 4E-4G further illustrate that that when onecomponent is selected in one design abstraction, the selected componentas well as its corresponding component may be graphically and/ortextually emphasized. In this example, a user selects one or more of theschematic circuit components 404A4, 406A4, and 408A4 in the schematicdesign (in FIG. 4F), the corresponding model 406C may also behighlighted in the extracted view in FIG. 4E and 406D in the modelannotator 400D as shown in FIG. 4G. Alternatively, a user may select themodel 406C in the extracted view illustrated in FIG. 4E (or the model“S3” (406D) in the model annotator 400D in FIG. 4G), and thecorresponding schematic circuit component designs 404A4, 406A4, and408A4 may be identified via the binding information described above andgraphically and/or textually emphasized in the schematic designillustrated in FIG. 4F.

As another working example of the binding between various abstractionsof the electronic design, a user may probe, for example, the eleventhnet (N11) 406A4 that is fully enclosed in the model 406C as two of thefour interfaces to the external circuitry. For example, a use may selectthe eleventh net 406A4 and instruct the system to provide electricalbehavior information such as a voltage value. Nonetheless, the built-inintelligence of the error handling process may find that this identifiednet for probing is fully enclosed in the model 406C and is thus not anappropriate target for probing by using, for example, the type of theidentified schematic circuit component design (a net) and the action tobe performed (a probing action). The error handling process may issue awarning message to so indicate in some embodiments. In some otherembodiments, the error handling process may further invoke an extractedview module to display at least the pertinent portion of thecorresponding model or model components.

FIG. 4H illustrates another example of another extracted view that maybe referenced for annotation of and binding with an electronic design inone or more embodiments. More specifically, FIG. 4H illustrates the sameextracted view as that illustrated in FIG. 4C or 4E.

FIG. 4I illustrates another example of a simplified schematic design towhich the model annotation and binding may be applied with reference tothe extracted view illustrated in FIG. 4H in one or more embodiments.More specifically, FIG. 4I illustrates the same schematic design as thatillustrated in FIG. 4A or 4F described above.

FIG. 4J illustrates another example of a simplified model annotationbrowser or model annotator for the extracted view illustrated in FIG. 4Hand the simplified schematic design illustrated in FIG. 4I in one ormore embodiments. More specifically, FIG. 4J illustrates the same modelannotator 400D as illustrated in FIG. 4D or 4G described above.

In this example, FIGS. 4H-4J further illustrate that that when onecomponent is selected in one design abstraction, the selected componentas well as its corresponding component may be graphically and/ortextually emphasized. In this example, a user selects one or more of theschematic circuit component 406A1 in the schematic design (in FIG. 4I),the corresponding model 402C may also be highlighted in the extractedview in FIG. 4H and 402D in the model annotator 400D as shown in FIG.4J. Alternatively, a user may select the model 402C in the extractedview illustrated in FIG. 4H (or the model “S1” (402D) in the modelannotator 400D in FIG. 4J), and the corresponding schematic circuitcomponent design 406A1 may be identified via the binding informationdescribed above and graphically and/or textually emphasized in theschematic design illustrated in FIG. 4I.

As another working example of the binding between various abstractionsof the electronic design, a user may probe, for example, the second net(N2) 406A1 that is incorporated into the model 402C as interfaces to theexternal circuitry. For example, a use may select the second net 406A1and instruct the system to provide electrical behavior information suchas voltage value. The identification of the second net 406A1 correspondsto more than one candidate voltage values so the system cannotdeterministically determine which voltage value to retrieve.

In some embodiments, the system may further inquire into which end ofthe second net (the first resistor end or the first capacitor end) theuser would like to obtain the electrical behavior information for. Insome other embodiments, the disambiguation module may provide bothvoltages at both ends of the second net 406A1 in response to theidentification of the second net. In some other embodiments, thedisambiguation module may further provide transient behavior information(e.g., waveforms) and/or distribution of the requested information alongthe identified schematic circuit component design. On the other hand, ifa user simply probes a pin in the schematic design, and the pincorresponds to a single physical pin, the system may retrieve thevoltage value at the physical pin from the analysis results and returnthe retrieved voltage value.

FIG. 4K illustrates an example of a schematic design and an extractedview that may be referenced for annotation of and binding with theschematic design in one or more embodiments. In this example, theschematic design includes a single logical pin for the Vcc pin 108K forthe first cell 124K and a single power pin for the second cell 126K. Theone or more computing systems 100A may invoke, for example, one or moreextracted view modules 120A to examine, for example, the layoutconnectivity information 110K or the optional electrical information114K that shows the Vcc pin is actually distributed among a plurality ofphysical pins 152K. Similarly, the one or more computing systems mayalso determine that the single logical power pin 112K1 is alsodistributed among a plurality of actual, physical pins.

These one or more computing systems 100A may create a first symbol forrepresenting the first cell as a first model in an extracted view and asecond symbol for representing the second cell as a second model in theextracted view. In some embodiments, a symbol may be created anew,whereas a symbol may be modified from an existing symbol (e.g., aschematic symbol of the first cell or the second cell). A symbolincludes appropriate interfaces to connect the model to the remainingportion of the electronic design. In this example illustrated in FIG.4K, the first symbol 128K is created for the first cell 102K andincludes five Vcc pins 134K that respectively correspond to the fiveactual, physical pins 152K. The second symbol 130K is also created forthe second cell 112K and includes four power pins 136K instead of asingle logical pin 112K1 as in the original schematic design.

Although FIG. 4K does not show, a symbol or even an extracted viewincluding the symbol may be further annotated with additional textualand/or graphical information comprising, for example, the identifiers ofcircuit component designs, physical, geometric, and/or electricalproperties of circuit component designs, etc. The original schematiccircuit component designs (102K and 112K) may be removed; and thesesymbols (128K and 130K) may be placed in the schematic design.

These symbols may further be interconnected with pertinent connectivityinformation using flight-line segments, orthogonal line segments, or acombination of one or more flight-line segments and orthogonal linesegments. In some embodiments, these symbols may be interconnected withschematic connectivity information. In some other embodiments, thesesymbols may be interconnected with layout connectivity information. Inother embodiments, one or more of these symbols may be interconnectedwith schematic connectivity information, and one or more remainingsymbols may be interconnected with layout connectivity information. Anextracted view 126K may then be stored at least temporarily in avolatile memory (e.g., random access memory) in some embodiments orpersistently in a storage device (e.g., a disk drive). It shall be notedthat an electronic design may concurrently correspond to more than oneextracted views each of which is bound or associated with the singleschematic design, the layout design, and the circuit component designsthereof.

With the extracted view 126K, a binding may be established between theextracted view and the schematic design 124K (or the electronic designin another extraction such as the layout). Moreover the schematic design124K may be back annotated with extracted view information pertaining tothe extracted view 126K. Some examples of such extracted viewinformation that may be back annotated into schematic designs areprovided in FIG. 4L described below.

FIG. 4L illustrates some examples of extracted view information that maybe annotated with or bound to an electronic design in one or moreembodiments. These examples of extracted view information that may beassociated with or annotated in an electronic design may includeelectrical, physical, and/or geometric information of circuit componentdesigns in the electronic design in some embodiments. In addition or inthe alternative, these examples may include information pertaining tothe layout 110K such as the power pin information 404L in a listing 402Lof circuit component designs pertaining to the physical pins 152K thatmay be represented as a single logical pin in the schematic design.

Analysis results 406L at various nodes or along various circuitcomponent designs in the electronic circuit design may also beassociated with or annotated in the corresponding nodes or portions ofthe electronic design. Moreover, the models 408L (e.g., s-parametermodels, transmission line models, IBIS models, SPICE sub-circuits, etc.)or information pertaining to the models may also be associated with orannotated in the electronic design.

Any of the annotated information may be presented either in theelectronic design (e.g., a schematic design) within close proximity ofthe corresponding circuit components or models or in a separate userinterface. These annotations can be further categorized into a pluralityof classes and even sub-classes (e.g., “physical”, “electrical”,“parasitic”, “waveforms”, etc.) so that the presentation of each classand sub-class may be individually configured to be displayed or hiddenin one or more user interfaces to avoid overly cluttering these one ormore user interfaces.

In addition, an electronic design may correspond to one or moreextracted views; and a node or a circuit component design (e.g., aschematic instance, a layout instance, etc.) may be annotated withmultiple values. For example, multiple analyses may be performed ondifferent extracted views having different models representing the sameor different circuit component designs therein. These multiple analysesthus provide analysis results having different accuracy. Some or all ofthese multiple analyses results may be annotated in the electronicdesign (e.g., a schematic design) in some embodiments. In some of theseembodiments, the most accurate result will be annotated in theelectronic design.

Some embodiments described herein provide schematic extracted views,bind a schematic extracted view with the schematic design, and enablethe user to view, manipulate, and probe the schematic design with thefull knowledge and awareness of the extracted view while the links orassociation between extracted views and the corresponding layouts aswell as the links or association between the extracted views and theschematic are preserved. These extracted views no longer have flat filestructures as conventional extracted views do. Instead, these extractedviews are generated and placed according to the hierarchies of thecircuit component designs these extracted views represent.

As a result, the extracted views may be arranged in a hierarchical datastructure where a parent (e.g., a model in an extracted view) at ahigher hierarchy may include one or more child circuit components at oneor more lower hierarchies. Moreover, a model in an extracted view may bebound to or associated with the circuit component designs that aremodeled in the model; and this model may be hierarchically placed in thehierarchical structure according to the hierarchical structure of theunderlying electronic design. This hierarchical structure of anextracted view may be presented in a window that enables a user toselect any entity (e.g., a model) at a hierarchy and expand or collapsethe hierarchy to view or hide its constituents.

When a user selects an entity from the hierarchical structure, thecircuit component design(s) in the schematic design corresponding to theselected entity may be highlighted or emphasized in the schematic designwindow. For example, a user may select a model in the hierarchicalstructure, and the schematic circuit component designs that correspondto this selected model may be graphically and/or textually emphasized inthe schematic design window that may be further optionally zoomed to anappropriate level to show the emphasized schematic circuit componentdesigns. In some embodiments where the extracted view is also showed(e.g., in a separate extracted view window), the model may also be shownin the extracted view. In other words, the hierarchical structure, theschematic design, the schematic design database or data structure, theextracted view(s) may be correlated with one another so that theidentification or selection of one entity in one may also be reflectedin the others.

In this manner, a user may visualize which schematic circuit componentdesigns have been represented as a specific model in the extracted view,and which schematic circuit component designs have not been representedas models in the extracted view. A model is generated not only forillustrating graphical resemblance with the schematic circuit componentdesigns for which the model is generated but also for providing moreinformation and more accurate information to simulation engines (e.g.,an electromagnetic solver) so that the simulation engines may moreaccurately predict the behaviors therefor. That is, a model describedherein is generated with graphical resemblance with the correspondingschematic circuit component designs as well as the layout components orinformation therefor while reducing or minimizing the impact on thegraphical resemblance due to the introduction of layout components. Someembodiments allow a user to pick and choose when and where in theschematic design more accurate simulation results are to be computed.

For example, a user may determine that a specific, smaller portion of aschematic design is of particular interest and thus need more accurateelectrical behavior. In this example, the user may invoke the processesdescribed herein to generate a model for these schematic circuitcomponent designs and an extracted view including at least this modelfor the schematic design. This extracted view may nevertheless includeschematic circuit component designs for which more accurate electricalbehavior is not needed or desired and thus have not been represented asmodel(s). This extracted view may then be provided to a simulationengine that solves for the predicted electrical behavior where thespecific, smaller portion represented by the model is more accuratelymodeled, yet another portion in the extracted view may not. Thesimulated electrical behavior is thus more accurate in the specific,smaller portion and may deviate more in another portion of the schematicdesign.

Moreover, representing a group of schematic circuit component designs asa model may be performed on the fly as permitted by the computationalpower and resources. Should the user decide that certain schematiccircuit component designs are to be represented as a model (e.g., moreaccurate simulation results are required or desired for these schematiccircuit component designs), the user may invoke the processes on the flyto create an extracted view for the schematic design having one or moremodels representing these schematic circuit component designs and sendthe extracted view to a simulation engine to obtain simulation resultswith different granularities or different levels of accuracy.

In this way, depending on the availability of computational resourcesand/or the objectives of predicting the electrical behavior of anelectronic design. For example, electrical behaviors with high accuracymay not be needed for concept and feasibility studies, and the extractedview may not need as many models representing the schematic circuitcomponent designs in the schematic design. On the other hand, electricalbehaviors before or during the layout implementation, forlayout-versus-schematic check, or before post-layout optimization mayrequire higher accuracy, and the extracted view therefor may thusinclude more models representing various schematic circuit componentdesigns.

An extracted view may be generated from the schematic as well as thelayout generated from the schematic in such a way to preserve or atleast resemble, to the extent possible, the graphical nature of theschematic design in some embodiments. This extracted view may be used toback annotate the schematic design from which the extracted view iscreated. Furthermore, a model may be generated for one or more schematiccircuit components (e.g., a trace, a resistor, a capacitor, an IC, orcombinations thereof, etc.) based at least in part upon the one or morecorresponding layout circuit components to model, for example, morecorrect parasitic, physical, and/or electrical characteristics. In someembodiments, a model may be generated as a transmission line model thatmay be further broken down into a network of inductance, capacitance,and/or resistance element(s).

A symbol may be generated for the model. This symbol may be generatedwith the same number of connection points or logical pins that theoriginal, one or more schematic circuit component designs use tointerface with the remaining portion of the schematic design. Theoriginal connections between the one or more schematic circuit componentdesigns in the schematic as well as the one or more schematic circuitcomponent designs may be removed from the schematic design. Thegenerated symbol may then be placed in lieu of these original one ormore schematic circuit design components.

In this simplified example having only one model representing one ormore schematic circuit component designs, a schematic view may begenerated, and the schematic design may then be associated with themodel. This association between the schematic design and the model maybe explicit as shown in the extracted view of the schematic design orimplicit where the users still see the original schematic designalthough the one or more components in the schematic design have beenrepresented with the model to simulation engines. Regardless of theimplicit or explicit nature of this association, the user may choosewhether the user would like to see the original schematic design or theextracted view that shows the model in place of the one or moreschematic circuit component designs; and the binding or associationbetween the one or more schematic circuit component designs (and hencethe schematic design) and the model always exist.

This extracted view may then be presented to a simulation engine thatsolves for the electrical behavior of this extracted view by using themodel. It shall be noted that this simplified example includes only onemodel for the ease of explanation and description although more modelsrepresenting more schematic circuit component designs may also beincluded in one or more other extracted views. That is, a schematicdesign may correspond to multiple extracted views each of which mayinclude a different number of models representing their respectiveschematic circuit component designs.

The simulation engine may then predict the behavior of the schematicdesign. In some embodiments where the binding and association areimplicit so the user operates directly on the schematic design, it shallbe noted that although the user may still see the one or more schematiccircuit component designs represented by the model, the behaviors ofthese one or more schematic circuit component designs are determined bythe model. In other words, if the user probes anywhere along the one ormore schematic circuit component designs, the corresponding solution(e.g., predicted behavior) is provided by the model.

As described above, a schematic design may be associated or bound withone or more extracted views each of which may include a different numberof models representing respective schematic circuit component designs.With an extracted view bound to a schematic design, a designer may probethe schematic design, and the claimed embodiments may identify the pointor portion corresponding to the probing point or portion in theschematic design from the bound or associated extracted view andretrieve and present the simulation results therefor to the designereven when the designer is directly operating on the schematic designwithout showing the extracted view.

In some embodiments where a designer probes a point in a schematicdesign, the claimed embodiments may react differently, depending uponwhere the probing point is. For example, when a designer probes a pin inthe schematic design, the claimed embodiments will show the electricalbehaviors from the simulation engine for the corresponding pin in theextracted view. When a designer probes a logic VDD, VCC, or GND pin inthe schematic design, the claimed embodiments may bring up thecorresponding detailed pin map that allow user either to view thedesired electrical behavior of all the physical pins associated with theprobed logic VDD, VCC, or GND pin in some embodiments or to select aphysical pin from the plurality of distributed physical pins and viewthe desired electrical behavior therefor.

When a designer probes a net in the schematic design, the claimedembodiments may show the desired electrical behavior (e.g., current,voltage values, etc.) for the corresponding net obtained from theextracted view. When a designer probes a device or a net in theschematic design, and the device or net is fully included in a model inthe extracted view, there will be no nodes for probing in the extractedview due to the full inclusion of the device or net in the model.Therefore, a message may show to indicate that probing at the selectedpoint or entity is not possible. On the other hand, probing a net ordevice that is replaced by a model in the extracted view may bring up adialogue box asking the designer to select which side of the net ordevice is to be probed. The claimed embodiments thus enable users toprobe waveforms from the schematic design, with or without showing theextracted view to the users.

System Architecture Overview

FIG. 5 illustrates a computerized system on which a method for bindingand annotating an electronic design with a schematic driven extractedview may be implemented. Computer system 500 includes a bus 506 or othercommunication module for communicating information, which interconnectssubsystems and devices, such as processor 507, system memory 508 (e.g.,RAM), static storage device 509 (e.g., ROM), disk drive 510 (e.g.,magnetic or optical), communication interface 514 (e.g., modem orEthernet card), display 511 (e.g., CRT or LCD), input device 512 (e.g.,keyboard), and cursor control (not shown). The illustrative computingsystem 500 may include an Internet-based computing platform providing ashared pool of configurable computer processing resources (e.g.,computer networks, servers, storage, applications, services, etc.) anddata to other computers and devices in an ubiquitous, on-demand basisvia the Internet. For example, the computing system 500 may include ormay be a part of a cloud computing platform in some embodiments.

According to one embodiment, computer system 500 performs specificoperations by one or more processor or processor cores 507 executing oneor more sequences of one or more instructions contained in system memory508. Such instructions may be read into system memory 508 from anothercomputer readable/usable storage medium, such as static storage device509 or disk drive 510. In alternative embodiments, hard-wired circuitrymay be used in place of or in combination with software instructions toimplement the invention. Thus, embodiments of the invention are notlimited to any specific combination of hardware circuitry and/orsoftware. In one embodiment, the term “logic” shall mean any combinationof software or hardware that is used to implement all or part of theinvention.

Various actions or processes as described in the preceding paragraphsmay be performed by using one or more processors, one or more processorcores, or combination thereof 507, where the one or more processors, oneor more processor cores, or combination thereof executes one or morethreads. For example, the acts of determination, extraction, stitching,simulating, annotating, analyzing, optimizing, and/or identifying, etc.may be performed by one or more processors, one or more processor cores,or combination thereof. In one embodiment, the parasitic extraction,current solving, current density computation and current or currentdensity verification is done in memory as layout objects or nets arecreated or modified.

The term “computer readable storage medium” or “computer usable storagemedium” as used herein refers to any non-transitory medium thatparticipates in providing instructions to processor 507 for execution.Such a medium may take many forms, including but not limited to,non-volatile media and volatile media. Non-volatile media includes, forexample, optical or magnetic disks, such as disk drive 510. Volatilemedia includes dynamic memory, such as system memory 508. Common formsof computer readable storage media includes, for example,electromechanical disk drives (such as a floppy disk, a flexible disk,or a hard disk), a flash-based, RAM-based (such as SRAM, DRAM, SDRAM,DDR, MRAM, etc.), or any other solid-state drives (SSD), magnetic tape,any other magnetic or magneto-optical medium, CD-ROM, any other opticalmedium, any other physical medium with patterns of holes, RAM, PROM,EPROM, FLASH-EPROM, any other memory chip or cartridge, or any othermedium from which a computer can read.

In an embodiment of the invention, execution of the sequences ofinstructions to practice the invention is performed by a single computersystem 500. According to other embodiments of the invention, two or morecomputer systems 500 coupled by communication link 515 (e.g., LAN, PTSN,or wireless network) may perform the sequence of instructions requiredto practice the invention in coordination with one another.

Computer system 500 may transmit and receive messages, data, andinstructions, including program (e.g., application code) throughcommunication link 515 and communication interface 514. Received programcode may be executed by processor 507 as it is received, and/or storedin disk drive 510, or other non-volatile storage for later execution. Inan embodiment, the computer system 500 operates in conjunction with adata storage system 531, e.g., a data storage system 531 that includes adatabase 532 that is readily accessible by the computer system 500. Thecomputer system 500 communicates with the data storage system 531through a data interface 533. A data interface 533, which is coupled tothe bus 506 (e.g., memory bus, system bus, data bus, etc.), transmitsand receives electrical, electromagnetic or optical signals that includedata streams representing various types of signal information, e.g.,instructions, messages and data. In embodiments of the invention, thefunctions of the data interface 533 may be performed by thecommunication interface 514.

In the foregoing specification, the invention has been described withreference to specific embodiments thereof. It will, however, be evidentthat various modifications and changes may be made thereto withoutdeparting from the broader spirit and scope of the invention. Forexample, the above-described process flows are described with referenceto a particular ordering of process actions. However, the ordering ofmany of the described process actions may be changed without affectingthe scope or operation of the invention. The specification and drawingsare, accordingly, to be regarded in an illustrative rather thanrestrictive sense.

We claim:
 1. A computer implemented method for binding and annotating anelectronic design with a schematic driven extracted view, comprising:identifying a schematic design and an extracted view of an electronicdesign; binding the schematic design or a portion of the schematicdesign with the extracted view and storing binding informationpertaining to binding the schematic design or the portion with theextracted view in a data structure, wherein the extracted view comprisesa schematic symbol of a first schematic component design and a model,and the extracted view is generated at least by removing the firstschematic component design from the schematic design and further byreplacing the first schematic component design in the schematic designwith the model; annotating, at an extracted view module stored at leastpartially in memory of and functioning in conjunction with amicroprocessor of a computing system, the schematic design withextracted view information pertaining to the extracted view based atleast in part upon the binding information; and generating a response toa user action based at least in part upon the extracted view informationor the binding information.
 2. The computer implemented method of claim1, further comprising identifying a layout of the electronic design,wherein the user action comprises a probing action that obtains one ormore electrical characteristics of the schematic design.
 3. The computerimplemented method of claim 1, generating the response to the useraction comprising: identifying a first user selection of a firstschematic circuit component design in the schematic design; andemphasizing a first model corresponding to the first schematic circuitcomponent design in the extracted view or a model tree structure inresponse to the first user selection.
 4. The computer implemented methodof claim 3, generating the response to the user action furthercomprising: identifying a second user selection of a second model in theextracted view; and emphasizing a second schematic circuit componentdesign corresponding to the second model in the schematic design or aschematic design tree structure in response to the second userselection.
 5. The computer implemented method of claim 1, generating theresponse to the user action comprising: identifying a schematic circuitcomponent design corresponding to the user action; identifying a modelcorresponding to the schematic circuit component design from theextracted view; and determining a type for the schematic circuitcomponent design.
 6. The computer implemented method of claim 5,generating the response to the user action comprising: identifying apoint of interest in the schematic design based in part or in whole uponthe type or the model that corresponds to the schematic circuitcomponent design; identifying one or more electrical characteristics atthe point of interest by using at least the extracted view; andpresenting the one or more electrical characteristics in a userinterface.
 7. The computer implemented method of claim 6, generating theresponse to the user action comprising: performing disambiguationprocessing in response to the user action based at least in part uponthe type for the schematic circuit component design.
 8. The computerimplemented method of claim 6, generating the response to the useraction comprising: performing error handling processing in response tothe user action based at least in part upon the type for the schematiccircuit component design.
 9. A system for binding and annotating anelectronic design with a schematic driven extracted view, comprising:non-transitory computer accessible storage medium storing thereuponprogram code; at least one micro-processor of one or more computingsystems that is configured to execute the program code to identify aschematic circuit and an extracted view of an electronic design; the atleast one micro-processor of one or more computing systems that isfurther configured to bind the schematic design or a portion of theschematic design with the extracted view and store binding informationpertaining to binding the schematic design or the portion with theextracted view in a data structure, wherein the extracted view comprisesa schematic symbol of a first schematic component design and a model,and the extracted view is generated at least by removing the firstschematic component design from the schematic design and further byreplacing the first schematic component design in the schematic designwith the model; an extracted view module that is stored at leastpartially in memory of the one or more computing systems, includes orfunctions in conjunction with the at least one micro-processor of theone or more computing systems, and is configured to execute the programcode to annotate the schematic design with extracted view informationpertaining to the extracted view based at least in part upon the bindinginformation; and the at least one micro-processor of one or morecomputing systems further configured to generate a response to a useraction based at least in part upon the extracted view information or thebinding information.
 10. The system for claim 9, wherein the at leastone microprocessor executing the program code to generate the responseto the user action is further configured to: identify a first userselection of a first schematic circuit component design in the schematicdesign; and emphasize a first model corresponding to the first schematiccircuit component design in the extracted view or a model tree structurein response to the first user selection.
 11. The system for claim 10,wherein the at least one microprocessor executing the program code togenerate the response to the user action is further configured to:identify a second user selection of a second model in the extractedview; and emphasize a second schematic circuit component designcorresponding to the second model in the schematic design or a schematicdesign tree structure in response to the second user selection.
 12. Thesystem for claim 9, wherein the at least one microprocessor executingthe program code to generate the response to the user action furtherexecutes the program code to: identify an interconnect from theschematic design; and identify one or more characteristics of theinterconnect, the one or more characteristics comprising signal risetime, one-way signal propagation time delay, an inductive impedance, ora resistance.
 13. The system for claim 9, wherein the at least onemicroprocessor executing the program code to identify the schematiccircuit component design further executes the program code to: identifya schematic circuit component design corresponding to the user action;identify a model corresponding to the schematic circuit component designfrom the extracted view; and determine a type for the schematic circuitcomponent design.
 14. The system for claim 13, wherein the at least onemicroprocessor executing the program code to identify the schematiccircuit component design further executes the program code to: identifya point of interest in the schematic design based in part or in wholeupon the type or the model that corresponds to the schematic circuitcomponent design; identify one or more electrical characteristics at thepoint of interest by using at least the extracted view; present the oneor more electrical characteristics in a user interface; and performdisambiguation processing in response to the user action based at leastin part upon the type for the schematic circuit component design.
 15. Anarticle of manufacture comprising a non-transitory computer accessiblestorage medium having stored thereupon a sequence of instructions which,when executed by at least one processor or at least one processor coreexecuting one or more threads, causes the at least one processor or theat least one processor core to perform a set of acts for binding andannotating an electronic design with a schematic driven extracted view,the set of acts comprising: identifying a schematic circuit and anextracted view of an electronic design; binding the schematic design ora portion of the schematic design with the extracted view and storingbinding information pertaining to binding the schematic design or theportion with the extracted view in a data structure, wherein theextracted view comprises a schematic symbol of a first schematiccomponent design and a model, and the extracted view is generated atleast by removing the first schematic component design from theschematic design and further by replacing schematic component design inthe schematic design with the model; annotating, at an extracted viewmodule stored at least partially in memory of and functioning inconjunction with a microprocessor of a computing system, the schematicdesign with extracted view information pertaining to the extracted viewbased at least in part upon the binding information; and generating aresponse to a user action based at least in part upon the extracted viewinformation or the binding information.
 16. The article of manufactureof claim 15, the set of acts further comprising: identifying a firstuser selection of a first schematic circuit component design in theschematic design; and emphasizing a first model corresponding to thefirst schematic circuit component design in the extracted view or amodel tree structure in response to the first user selection.
 17. Thearticle of manufacture of claim 16, the set of acts further comprising:identifying a second user selection of a second model in the extractedview; and emphasizing a second schematic circuit component designcorresponding to the second model in the schematic design or a schematicdesign tree structure in response to the second user selection.
 18. Thearticle of manufacture of claim 15, the set of acts further comprising:identifying a schematic circuit component design corresponding to theuser action; identifying a model corresponding to the schematic circuitcomponent design from the extracted view; and determining a type for theschematic circuit component design.
 19. The article of manufacture ofclaim 18, the set of acts further comprising: identifying a point ofinterest in the schematic design based in part or in whole upon the typeor the model that corresponds to the schematic circuit component design;identifying one or more electrical characteristics at the point ofinterest by using at least the extracted view; and presenting the one ormore electrical characteristics in a user interface.
 20. The article ofmanufacture of claim 19, the set of acts further comprising at least oneof: performing disambiguation processing in response to the user actionbased at least in part upon the type for the schematic circuit componentdesign; or performing error handling processing in response to the useraction based at least in part upon the type for the schematic circuitcomponent design.